Ken Turner - Online Hardware Description and Validation Publications

These papers are available for downloading. See also the separate lists of publications on other topics. Click on the symbol preceding each article for the following:

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Hardware Description and Validation

F. Javier Argul-Marin and Kenneth J. Turner. Extending Hardware Description in SDL. Technical Report CSM-155, Department of Computing Science and Mathematics, University of Stirling, Scotland, February 2000.

Gyula Csopaki and Kenneth J. Turner. Modelling Digital Logic in SDL. In Tadanori Mizuno, Norio Shiratori, Teruo Higashino and Atsushi Togashi, editors, Proc. Formal Description Techniques X/Protocol Specification, Testing and Verification XVII, pages 367-382, Chapman and Hall, London, UK, November 1997.

Ji He and Kenneth J. Turner. Extended DILL: Digital Logic in LOTOS. Technical Report CSM-142, Department of Computing Science and Mathematics, University of Stirling, Scotland, November 1997.

Ji He and Kenneth J. Turner. Timed DILL: Digital Logic in LOTOS. Technical Report CSM-145, Department of Computing Science and Mathematics, University of Stirling, Scotland, April 1998.

Ji He and Kenneth J. Turner. Modelling and Verifying Synchronous Circuits in DILL. Technical Report CSM-152, Department of Computing Science and Mathematics, University of Stirling, Scotland, April 1999.

Ji He and Kenneth J. Turner. Protocol-Inspired Hardware Testing. In Gyula Csopaki, Sarolta Dibuz and Katalin Tarnay, editors, Proc. Testing Communicating Systems XII, pages 131-147 (revised version), Kluwer Academic Publishers, London, UK, September 1999.

Ji He and Kenneth J. Turner. Specification and Verification of Synchronous Hardware using LOTOS. In Jianping Wu, Samuel T. Chanson, Quiang Gao, editors, Proc. Formal Methods for Protocol Engineering and Distributed Systems (FORTE XII/PSTV XIX), pages 295-312, Kluwer Academic Publishers, London, UK, October 1999

Ji He and Kenneth J. Turner. Verifying and Testing Asynchronous Circuits using LOTOS (extended version). In Tommaso Bolognesi and Diego Latella, editors, Proc. Formal Methods for Protocol Engineering and Distributed Systems (FORTE XIII/PSTV XX), pages 267-283, Kluwer Academic Publishers, London, UK, October 2000

Ji He and Kenneth J. Turner. Specifying Hardware Timing with ET-LOTOS (extended version of article published by and copyright Springer-Verlag). In Tiziana Margaria and Thomas F. Melham, editors, Proc. 11th Conference on Correct Hardware Design and Verification Methods (CHARME 2001), Lecture Notes in Computer Science 2144, pages 161-166, Springer Verlag, Berlin, Germany, September 2001.

Kenneth J. Turner. An engineering approach to formal methods. In Andre A. S. Danthine, Guy Leduc, and Pierre Wolper, editors, Proc. Protocol Specification, Testing and Verification XIII, pages 357-380. North-Holland, Amsterdam, Netherlands, June 1993.

Kenneth J. Turner and Ji He. Formally-Based Design Evaluation (extended version of article published by and copyright Springer-Verlag). In Tiziana Margaria and Thomas F. Melham, editors, Proc. 11th Conference on Correct Hardware Design and Verification Methods (CHARME 2001), Lecture Notes in Computer Science 2144, pages 104-109, Springer Verlag, Berlin, Germany, September 2001.

Kenneth J. Turner, F. Javier Argul Marin and Stephen D. Laing. Concurrent Specification and Timing Analysis of Digital Hardware using SDL (extended version of article published by and copyright Springer-Verlag). In Jose Rolim et al., editors, Proc. International Parallel and Distributed Processing Symposium, Cancun, Mexico, LNCS 1800, pages 1001-1008, Spring Verlag, Berlin, Germany, May 2000.

Kenneth J. Turner and Richard O. Sinnott DILL: Specifying digital logic in LOTOS. In Richard L. Tenney, Paul D. Amer, and M. Ümit Uyar, editors, Proc. Formal Description Techniques VI, pages 71-86. North-Holland, Amsterdam, Netherlands, 1994.

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