ANISEED (Analysis In SDL Enhancing Electronic Design)



ANISEED (Analysis In SDL Enhancing Electronic Design) is a collaborative project led by Ken Turner (University of Stirling) and Gyula Csopaki (Technical University of Budapest). The project also involves Gusztáv Adamis (Technical University of Budapest), Alan Hamilton (University of Stirling) and Tamás Kasza (Technical University of Budapest). Past contributors have included Javier Argul-Marin and Stephen Laing (University of Stirling).

Initial project work was supported by COST 247, the British Council and the Hungarian Prime Minister's Office, enabling four visits by Gyula Csopaki to Stirling between July 1996 and March 1997. The Foundation Pro Renovatio Culturae Hungariae and the Schlumberger Foundation supported continuation of the work, allowing a visit by Ken Turner to Budapest in May/June 1998. The work is currently being supported by NATO under grant HTECH.CRG974581, from January 1999 to December 2000.

Traditional computer system design makes a sharp distinction between hardware and software. This is undesirable because the decision as to which functions should be in hardware or software should be left as late as possible. It is advantageous to use formal (mathematical) methods in computer system design to permit precise specification, systematic analysis and rigorous development. Telecommunications systems are an intricate mix of hardware and software that need rigorous design methods. The project combines the expertise of the collaborators to develop a rigorous hardware-software co-design approach using SDL (Specification and Description Language, ITU Z.100). The objectives of the project are:

SDL is an internationally standardised technique for specifying, analysing and implementing sequential, concurrent or distributed systems. It has been particularly developed for and applied to telecommunications systems design. Although there has been work on using SDL for digital logic design and hardware-software co-design, this application of SDL is relatively undeveloped. Most work in this field has concentrated on hardware synthesis via VHDL (VLSI Hardware Description Language).


Hardware Specification Languages are widely used; VHDL and Verilog are major international standards among these. FDTs (Formal Description Techniques) such as LOTOS (Language Of Temporal Ordering Specification) and SDL are also used as hardware specification languages. Because LOTOS and SDL are system description languages, they can be used for hardware-software co-design too. The LOTOS-based approach is called DILL (Digital Logic in LOTOS). The approach is realised as a language and set of tools. DILL supports the hardware engineer when translating a circuit schematic into a LOTOS specification. The DILL library contains pre-defined components and they can be used as building blocks. The ANISEED approach is somewhat similar in spirit to DILL except that the specification language is SDL. The designer needs only a basic knowledge of SDL in order to specify and analyse circuits.

A methodology for specifying digital logic in SDL has been elaborated by the collaborators. This supports multi-level specifications of hardware behaviour and structure, exploiting features of SDL-92. At the higher level of specification, event structures support specification of event sequences (e.g. one-of/all-of event structures) and event patterns with timing restrictions.

The behaviour of a hardware functional unit is specified by a block type. Block types are used to represent generic components; actual components are instances of these. All of the components are stored in SDL packages that can be used as a library. When the generic definition of a component is instantiated, its parameters are set to specify the characteristics of the particular instance. Parameters include the names of input and output signals, as well as timing characteristics such as propagation delays. A circuit design usually employs a number of components. Processes are therefore combined in an SDL block type. An SDL block type consists of processes that represents a component. Connections between blocks are made via SDL gates.


The main work to date has been to define an approach for (un)timed specification of hardware components in SDL. Specifications may be written at various levels of abstraction (abstract ordering/temporal constraints, behavioural specification, structural specification). Specifications may also use uni-bit or multi-bit signals (e.g. for buses). The approach has been embodied in a library of SDL packages that define block types for the components. Tools allow library packages to be generated automatically using a macro processor. This allows maximum commonality since similar components are described just once and then instantiated in various forms (time/untimed, uni/multi-bit, levels of abstraction, number of inputs, logic function). CIF (Common Interchange Format) and PR (Phrasal Representation) comments are generated automatically in order to enhance usability of the libraries.

Work so far has focused on the following aspects:

Digital Logic Library
A substantial library with about 400 elements has been developed for a range of typical components specified in SDL. The components are specified at various levels of abstraction and in timed/untimed forms. Much of the library consists of variants on basic components. These variants are generated automatically, allowing the core library to be much smaller and more maintainable.

Timing Analysis Simulator
A discrete event simulation has been developed for circuit timing analysis. In fact this is mainly achieved by an intelligent scheduler that is integrated with a standard SDL tool (Telelogic SDT). Validation output is generated in the form of MSCs (Message Sequence Charts) that are converted to the more usual timing sequence diagrams used by engineers.

Circuit Validation
Circuits are validated partly through manual simulation and partly through scenarios expressed as MSCs. These scenarios are manually generated or are automatically produced from simulation runs. The latter is particularly useful when checking correct refinement of designs at different levels of abstraction.

Future work will include using SDL at higher (architectural) levels of circuit design, verification of timing properties, and hardware-software co-design.


The following papers provide technical details of the work:

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Last Update: 15th July 2006